Exemplary embodiments relate to preventing cracks in electronics, and particularly to protecting traces against cracking.
In microelectronics, the ball grid array (BGA) is replacing pin grid array (PGA). The BGA descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern. These pins are used to conduct electrical signals from the integrated circuit that it is placed on top a printed circuit board (PCB). In a BGA, however, the pins are replaced by balls of solder stuck to the bottom of the package (device). The device is placed on a PCB that carries copper pads in a pattern that matches the solder balls. The assembly is then heated, either in a reflow oven or by an infrared heater, causing the solder ball to melt. Surface tension causes the molten solder to hold the package in alignment with the circuit board, at the correct separation distance, while the solder cools and solidifies. Many devices now utilize the BGA in the assembly process.
For example, FCPBGA (Flip Chip Plastic Ball Grid Array) substrates are typically constructed from multiple layers of copper circuitry separated by organic dielectrics. These build-up layers of circuitry and dielectric are deposited on either side of a fiber reinforced resin core. The fibers in the core are typically in the form of woven glass cloth, although non-glass and/or non-woven fiber reinforcements are also used in the industry. The build-up dielectrics are typically based on organic resins typically do not contain fiber reinforcements, but do not contain inorganic and organic filler particles to reduce the coefficient of thermal expansion (CTE). Since the build up dielectrics do not contain fiber reinforcement, they are prone to crack initiation and propagation when subjected to cyclic tensile strains. Such cyclic tensile strains result from the bonding together of materials with widely differing CTEs within the laminate substrate and assembled module. Typical materials of construction are Cu(CTE=˜17 ppm/° C.), core dielectric (CTE=˜12 to 20 ppm/° C.), silicon (CTE=˜3 ppm/° C.), and build-up dielectric (CTE=˜45 to 90 ppm/° C.). During thermal cycling the materials try to expand and contract at different rate, but because they are bonded together in a layered structure, the expansion and contraction of each material is constrained by other materials, resulting in strains within the materials. Under some conditions these strains have been observed to cause cracking of the build-up dielectrics.
In FCPBGA packages, dielectric cracks are often initiated at the periphery of the Cu BGA pads on the bottom surface of the module, and propagate essentially perpendicular to the major plane of the structure. Crack propagation slows or terminates when the crack reaches a layer that is more resistant to cracking than the build-up dielectric. This crack interrupting layer is usually either a large planar area of Cu or the fiber reinforced core dielectric. In extreme cases, there is sufficient strain energy to cause crack propagation through either large areas of Cu or into the core dielectric.
In microelectronics, traces (lines) need to be protected against cracking. As mentioned above, the cracking is usually propagated in the laminate and initiated from the ball grid array (BGA), and thus, without protection, the traces can be broken.
Therefore, features are needed to protect traces from cracking in microelectronics.